Memory devices typically are composed of an array of bit cells, with each bit cell having a storage component to store or retain an electrical charge representative of a bit value (e.g., a logic “0” or a logic “1”). However, due to the electrical properties of the bit cells, memory devices typically can operate with relatively low power consumption or at relatively high speed, but not both. Further, memory architectures that operate with relatively low power consumption or operate at relatively high speeds typically are difficult to scale. Flash memories, for example, exhibit relatively low power consumption and are relatively easy to scale but are relatively slow in comparison to other memory architectures, such as static random access memories (SRAMs), which are relatively fast but often are difficult to scale and typically do not operate reliably in low power implementations. Accordingly, an improved technique for storing and retaining data would be advantageous.
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